| 摘要 |
<p>A digital data multiple conversion system includes a memory unit (21) storing input data (IN-DATA) having N bits, a first frequency divider (23) frequency-dividing an input clock (IN-CLK) having a first frequency (f1) at N to output a first frequency-divided signal (S23), a first pulse width expansion circuit (25) connected to receive m frequency divided pulses from the first frequency divider, where m indicates the number of lost pulses of the input clock plus one receiving the input clock, and outputting a first pulse width expanded signal (S25) of the input clock having an m + 1 pulse width, a circuit (22) outputting a read clock having a second frequency (f1') near to the the first frequency (f1) and stuffing the read clock, a second frequency divider (24) frequency-dividing the read clock at N to output a second frequency-divided signal (S24), a second pulse width expansion circuit connected to receive n frequency divided pulses from the second frequency divider, where n indicates the number of lost pulses of the read clock plus one, receiving the read clock, and outputting a second width expanded signal of the read clock having an n + 1 pulse width; a phase detector (27) outputting a phase detection signal (S27) when the phases of both pulse width expanded signals coincide, and a stuffing request circuit (28) outputting a stuffing request signal (S28) to the stuffing circuit (22). The stuffing circuit (22) stuffs the read clock in response to the stuffing request signal (S28). The memory unit (21) stores the input data in response to the first frequency-divided signal (S23), and outputs the stored data to the stuffing circuit (22) in response to the second frequency-divided signal (S24).</p> |
