发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To support plural architectures by one microprogram by providing the titled device with a means indicating the status of the architecture to be executed. CONSTITUTION:When a switching bit X12 in a program status word PSW11 is ''0'', a BC mode is specified. In instruction branching (OP branch) at that time, an adder 13 addes 0000 to a branch address. Namely, the address is branched as the original branch address itself to an OP table A15. When the switching bit X12 is ''1'', an EC mode is specified. At the OP branching, 1000 is added to the address to be branched to the OP table A15 and the added address is branched to an OP table B16. IF architecture switching information is provided to the PSW11, an address can be branched to plural OP tables without forming new OP codes by using said information.
申请公布号 JPS59112345(A) 申请公布日期 1984.06.28
申请号 JP19820222077 申请日期 1982.12.20
申请人 FUJITSU KK 发明人 SASOU HIDEYUKI;SATOU NOBUYOSHI;SAKURAI MITSUO
分类号 G06F9/22;G06F9/26;G06F9/318;G06F9/38;(IPC1-7):06F9/26 主分类号 G06F9/22
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