发明名称 CLOCK EXTRACTING CIRCUIT
摘要 PURPOSE:To decrease external parts and the number of pins, and to facilitate the IC integration by using a switched capacitor filter for a top filter of a PLL for controlling an LPF for obtaining a comparing signal of a comparator by smoothing a digital signal, and a VCO for giving the amplitude and the phase characteristic required for an output of a phase comparator. CONSTITUTION:A DC component of an RF signal from a reproducing device is eliminated by an HPF 1, a digital signal is inputted to a comparator 2, and a high frequency component is eliminated by an LPF 3. An output signal of this LPF 3 is inputted as a comparing signal to the comparator 2 through a switch capacitor filter SCF 4. Also, the output of the comparator 2 is inputted to a phase comparator 5, and supplied to the phase comparator 5 by a PLL by an LPF 6, an SCF 7, a VCO 8 and a frequency divider 9. These SCFs 4, 7 are constituted of switches 21, 22, capacitors 23, 24 whose capacities are C1 and C2, and an operational amplifier 25, the number of external parts and pins is decreased, and the IC integration of a clock extracting circuit is facilitated.
申请公布号 JPS63227120(A) 申请公布日期 1988.09.21
申请号 JP19870060637 申请日期 1987.03.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YASUDA HIROSHI;NAKAMURA MASAYOSHI;HARUI MASANORI;KOBA MASAO;NISHIOKA AKIHIKO
分类号 G11B20/14;H03L7/08;H03L7/093 主分类号 G11B20/14
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