| 摘要 |
PURPOSE:To detect at a high speed a variation picture element address by providing plural mask circuits to which a variation picture element is inputted simultaneously, and plural decoder circuits to which data from the mask circuits is inputted simultaneously. CONSTITUTION:When an image data D is inputted to a variation picture element detecting circuit 7, a variation picture element data C in which a bit corresponding to a variation picture element of the data D is '1' and a bit corresponding to other picture element is '0' is outputted. It is latched by a latching circuit 9. In this case, a mask data M1 in which only a bit corresponding to the lowest bit of '1' contained in a picture element data outputted from the circuit 9 is '0' is outputted from a mask circuit 10, therefore, a variation address corresponding to this '0' bit is outputted from a decoder circuit 12. Also, a mask data M2 in which only a bit corresponding to the second lower bit of '1' contained in the data outputted from the circuit 9 is '0' is outputted from a mask circuit 11, therefore, a variation picture element address corresponding to this '0' bit is outputted from a decoder circuit 13.
|
