发明名称 BINARY DATA COMPRESSION/EXPANSION PROCESSOR
摘要 PURPOSE:To execute a processing at a high speed by providing a barrel shifter between a register for holding the image data of a reference line and a b1 point detecting circuit. CONSTITUTION:A decoding part 2 executes decoding of the image data obtained from an input bus 9 at the time of expansion, detects a variation point from the same data at the time of compression, and also, obtains the line length. In a processing part 4, a barrel shifter inputs the image data through a reference line holding means, and also, inputs position information of an a0 point which has been held by an a0 point position holding means. Subsequently, the image data is shifted to a reverse processing direction side, in accordance with the position information of the a0 point, so that the bit which has been extended by >=4 bits in the reverse processing direction from the extreme left side of a point position range of a0 set to the same means, and has been extended by >=3 bits in the processing direction from the extreme right side becomes a variation point detecting object. A b1 point detecting means detects a veriation point from the shifted image data. Accordingly, to the b1 point detecting means, the image data whose variation point detection is not required is not inputted, therefore, the processing can be executed at a high speed.
申请公布号 JPS63227177(A) 申请公布日期 1988.09.21
申请号 JP19870059990 申请日期 1987.03.17
申请人 TOSHIBA CORP 发明人 SATO FUMITAKA;MURAYAMA MASAYOSHI
分类号 H04N1/413 主分类号 H04N1/413
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