Memory unit.

摘要

A memory unit includes a dual port memory (15) provided with a RAS input terminal and a WB/WE input terminal adapted to receive a RAS clock signal and a bit select clock signal, respectively. A first signal generator (17) generates the RAS clock signal and the bit select write signal at a timing at which the dual port memory (15) performs the normal write operation, whereas the bit select write operation is carried out in response to clock signals supplied from a second signal generator (18) at another timing. A selective one of the first and second signal generators (17,18) is made operative in response to at least one bit mode-specifying data supplied from CPU (11). Both of the first and second signal generators receive a continuous signal from CPU so that they are in a position to send the signals of different timings to the dual port memory responsive to the mode-specifying data.