Array-word-organized display memory and address generator with time-multiplexed address bus

摘要

An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of the RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of the CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.