| 摘要 |
PURPOSE:To improve the reliability of an integrated circuit by suppressing a rise in the GND potential in the integrated circuit when numbers of output circuits are driven at the same time. CONSTITUTION:When a signal having a value ''1'' is supplied to an input terminal T1, PMOS transistors(TR) M3-M5 turn on and NMOSTRs M6-M8 turn off, so a charging current I'1 flows to an external load capacitor CL. When a signal having a value ''0'' is supplied to the input terminal T1, on the other hand, the PMOSTRs M3-M5 turn off and the NMOSTRs M6-M8 turn off, so a discharging current I'2 flows from the external load capacity CL to the integrated circuit GND. At this time, the NMOSTRs M6-M8 are connected to the path through which the load capacitor CL is discharged, so the ON resistance increases to reduce the current which flows into the integrated circuit GND in every unit time. Therefore, variation in current per unit time decreases, so a rise in potential due to the inductance of a GND line is reduced. Consequently, the integrated circuit having high reliability is obtained. |
