发明名称
摘要 A frequency synthesizer of the type which selects pulses from a clock pulse generator (21) to provide a lower output frequency Fo, the synthesizer including an accumulator (22) of the type which, for each input pulse thereto, adds a preselected increment Y to the accumulated value in the accumulator and gives an overflow pulse each time an accumulated value C (where C is equal to or greater than Y) is reached or exceeded and leaves any excess (residue) in the accumulator. In accordance with the invention, adjustable delay means are coupled to the accumulator output such that each output pulse is delayed by an amount which depends on the residue in the accumulator thereby providing a spectrally pure output frequency.
申请公布号 JPS6347013(B2) 申请公布日期 1988.09.20
申请号 JP19800150863 申请日期 1980.10.29
申请人 FUIRITSUPUSU FURUUIRANPENFUABURIKEN NV 发明人 MAIKERU JEIMUSU ANDAAHIRU;RICHAADO AIAN HINDOREI SUKOTSUTO
分类号 H03K23/64;H03K21/00;H03K23/66 主分类号 H03K23/64
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