| 摘要 |
PURPOSE:To facilitate the synchronization detection by detecting and correcting the dissidence data in M-bit included in a decision output of N-bit in a prescribed order and deciding it that no synchronizing code is detected when no dissident data is detected. CONSTITUTION:An input signal series including an 8-bit synchronizing code series inputted from a signal input terminal 1 is converted into a parallel signal by an 8-bit shift register 2. EX-NOR circuits 5-1-5-8 detect the coincidence of each bit of a preset synchronizing code pattern and gives the result to a 3-bit data generating circuit 20. The output of the circuit 20 is fed to an 8-bit data generating circuit 21 via inverters 22-24 and the output of the circuit 21 is fed to OR circuit 25-1-25-8 together with the output signal from the circuits 5-1-5-8 to correct the dissidence signal from the circuit 20. The signal not corrected is given to an AND circuit 8, and an OR circuit 28 outputs a signal representing the result of detection of the synchronizing code when no dissidence data is detected to an output terminal 4. |
