| 摘要 |
PURPOSE:To latch an input data without error by using a delay clock generated from an output clock from a clock switching means so as to latch an input data and switching the phase of the output clock when the dissident number reaches a prescribed value. CONSTITUTION:A latch/error detection means 4 uses an output clock from a clock switching means 6 to generate clocks with different phase and the input data is extracted by the generated clock and latched. The latched data are compared mutually to detect whether or not they are coincident and the dissidence is counted by an error count means 5. When the count reaches a prescribed value, a clock switching means 6 is driven by a drive signal sent therefrom automatically and the phase of the output clock is shifted by a prescribed quantity. Thus, the input data is latched without error. |
