| 摘要 |
PURPOSE:To make the titled circuit most suitable for large scale circuit integration by devising the titled circuit such that number of bits required to receive/ transmit a signal between a storage circuit being an externally mounted circuit and the circuit being an abject of LSI is reduced remarkably in comparison with a conventional circuit. CONSTITUTION:A timing generating circuit 3 generates a clock comprising a clock pulse number corresponding to the total bit number of decision threshold values of, e.g., 7 values in response to a start signal being an external input and gives it to an address counter 2 and a shift register 4. The counter 2 sends each decision threshold value corresponding to a ratio Eb/N0 being a ratio of an energy per one bit of transmission signal to one side noise power density N0 of a communication line by the external designation from a ROM 1 serially. Then, the register 4 fetches each decision threshold value to be outputted according to the clock and outputs each of them to other input of comparators 22-28. Thus, the address count value of the ROM 1 is enough to be 8-bit while the required bit number is to be 7X31(=217).
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