| 摘要 |
PURPOSE:To always locate the edge of a clock at the center of a pulse width by retarding the output of a 1st delay circuit by a 2nd delay circuit for a prescribed time, and outputting AND or OR of outputs of the 1st and 2nd delay circuits. CONSTITUTION:The delay time of delay elements 11-14 of a delay circuit 10 is set to T and the delay time of delay elements 21-24 of a delay circuit 20 is set to 2T. A switch 32 is switched in interlocking with a switch 31. The input stage of the element 14 and the output stage of the element 21 are selected, then the output of the switch 31 is advanced by a time T more than the output of the element 14. Since the pulse is delayed by the element 21 by a time 2T, the output of the switch element 32 is delayed by the time T with respect to the output of the element 14. Thus, in operating outputs of the switches 31, 32 by an AND gate 33, a pulse where the clock edge is located at the center and the preceding and succeeding edges are narrowed by the time T is generated. Similarly, a pulse where the clock edge is located at the center and the preceding and succeeding edges are widened by the time T is generated at the output of an OR gate 34. |
