| 摘要 |
PURPOSE:To delay the fall of a command signal and to increase the set-up time between the switch of the address signal and the fall of the command signal, by setting a wait signal active when the command signal is inactive. CONSTITUTION:In a command generating circuit, an AND circuit A serve as inputs and a wait signal WT1 is inputted to one of these inputs via a signal line l. A requester turns on a start signal SRT (H level) when the signal WT1 is kept at an H level. Thus an ANDSA is immediately set at an H level and a command signal CMD is outputted with the next clock signal CLK. In case the signal WT1 is set at an L level before the signal SRT is turned on, the AND output SA is set at L level. Thus the signal CMD is never set at an L level before the signal WT1 is set at an H level. In such a way, the fall of the signal CMD is delayed and at the same time the pulse width is increased with addition of a single signal line l.
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