发明名称 BUS ARBITRATING CIRCUIT
摘要 PURPOSE:To perform the fast arbitration of buses via a simple circuit according to the output characteristics of an open collector. CONSTITUTION:When a bus application request signal 11 is inputted, a recognizing signal generating circuit 12 produces a signal group so that the low and high level signals are increased one by one with modules having high and low bus application priorities respectively. An arbitrating signal line group 15 consists of signal lines in the number larger than the number of modules using buses. An open collector output circuit 13 outputs the recognizing signal produced by the circuit 12 to the group 15. In case plural modules have the bus application requests, the signal obtained from collision between signals of high and low levels is set at a low level since the output of an open collector is given to the group 15. Therefore a comparator 14 of the module having the highest priority among those modules having bus application request obtains the coincidence between the signal produced by the circuit 12 and the signal set on the group 15 and outputs a bus application permitting signal 16.
申请公布号 JPS63223853(A) 申请公布日期 1988.09.19
申请号 JP19870057121 申请日期 1987.03.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KITAMURA TOMOHIKO;TERAI HIDEO;NAKAO MITSUTOSHI;KONO YASUFUMI
分类号 G06F13/368;G06F13/26;G06F13/374 主分类号 G06F13/368
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