| 摘要 |
PURPOSE:To reduce an error, and also, to execute a processing at a high speed by executing in parallel a calculation, by selecting and outputting a result of calculation of the effective data block concerned at the time point when three states consisting of a carry and a sum of a rounding correction use block have been determined, by an adding circuit for outputting a rounding result conforming to word length. CONSTITUTION:Correction use parts AL, BL of input data A, B are added by a two input adder 1, and a sum 11 of the uppermost digit and a carry 12 sent to the higher rank from the uppermost digit are calculated. Its respective signals are added by a selecting signal generating circuit 2, and become a selecting signal of a 3-1 selector 4. Also, AH and BH corresponding to effective data word length of data A, B are inputted to two input adders 30, 31 and 32, and AH+BH, AH+BH+1 and AH+BH+2 are calculated, respectively. Outputs calculated by said each adder 30, 31 and 32 are inputted to the selector 4, output signals of the adders 30, 31 and 32 are selected by the selecting signal from the circuit 2, and one of results of calculation of an effective data block is selected. |
