发明名称 LOGIC DIAGRAM EXECUTION ROUTE OUTPUT PROCESSING SYSTEM
摘要 PURPOSE:To easily understand the flow of control in a logic diagram source by displaying the logic diagram source being a debug object, in a form by which an execution route goes to clear. CONSTITUTION:Each execution sentence of a logic diagram source and address information of a debug object program being a target are allowed to correspond to each other in advance by discontinuing management table 18. An execution processing part 20 detects an address of a discontinued target from the table 18, and obtains its source line number. An execution frequency column of an entry of the table 18 having this line source number is updated, and a history of an execution route is managed. At the time of displaying the logic diagram source by a notice from the processing part 20, a display processing part 22 checks the table 18, emphasizes and displays a control line 31 of an executed line, and indicates clearly the execution route. Accordingly, the flow of a control of the logic diagram source can be understood easily.
申请公布号 JPS63223931(A) 申请公布日期 1988.09.19
申请号 JP19870058558 申请日期 1987.03.13
申请人 FUJITSU LTD 发明人 TSUBOKURA TOKIHIKO;TAKADA CHIHARU
分类号 G06F11/32;G06F9/44;G06F9/45 主分类号 G06F11/32
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