| 摘要 |
PURPOSE:To reduce the circuit scale of a vertical synchronous separating circuit with high quantization accuracy by synchronizing a composite synchronizing signal with clock pulses of sufficiently high frequency, resetting a means which divides the frequency of a high-accuracy clock with its synchronized output, and using its frequency division output as the clock of an up/down counting means. CONSTITUTION:The composite synchronizing signal A is synchronized by D flip-flop circuits 31 and 32 and an inverter 40 with the clock pulse C. An AND circuit 41 detects one edge, e.g. leading edge of the synchronized composite synchronizing signal A and D flip-flop circuits 33-35 are reset with the detection output. When an all-'0' state is detected, a D flip-flop circuit 36, AND circuits 44 and 45, and an inverter 45 inhibit a clock for counting from being inputted to the up/down counter 37 to stop its counting operation. An AND circuit 42 resets the D flip-flop circuit 36 with the leading edge of the composite synchronizing signal A synchronized with the clock pulses C to reset the stop of the counting operation.
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