发明名称 COMPLEMENTARY MIS TYPE INTEGRATED CIRCUIT AND MANUFACTURE THEREOF
摘要 PURPOSE:To suppress a short channel effect, to improve punch-through breakdown voltage and to make it possible to implement minute P-MOS, by increasing the impurity concentration in the surface of an Si substrate forming the P-MOS. CONSTITUTION:Sb ions or As ions are implanted into the surface of an N-type Si substrate 1 to form an N-type region 16 whose impurity concentration is higher than that of the substrate 1. Then a P-well region 2 is formed. A P-MOS 20 and an N-MOS 30 are formed by an ordinary method. The diffusion coefficient of B, which is implanted for forming the source and the drain of the P-MOS 20, is larger than the diffusion coefficient of As ions which are implanted for forming the source and the drain of the N-MOS 30. Since the P-MOS 20 is formed in the high impurity concentration region 16, a short channel effect is suppressed. Since the punch-through breakdown voltage of the P-MOS 20 can be improved, the P-MOS 20 can be miniaturized.
申请公布号 JPS63222455(A) 申请公布日期 1988.09.16
申请号 JP19870055637 申请日期 1987.03.11
申请人 MATSUSHITA ELECTRONICS CORP 发明人 YAMAOKA TORU
分类号 H01L21/8238;H01L27/092 主分类号 H01L21/8238
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