发明名称 RECEPTION BUFFER MANAGEMENT EQUIPMENT
摘要 PURPOSE:To use a buffer while packing its memory from its end by discriminating the necessity of a received frame and resetting the address generating circuit designating the address of the reception buffer to be restored in case of an undesired frame. CONSTITUTION:A sequence circuit 4 selects the 1st buffer 5 and the 2nd buffer 7 alternately for each reception frame and gives a signal to corresponding address generating circuits 6, 8. The address generating circuit gives an address to each buffer and stores a reception frame. A discrimination controller 9 reads a control information area written in a specific location of the reception frame from the buffer received just now and gives a reset signal to the corresponding address generator 6 or 8 when an unrequired frame is discriminated. The address generation circuit restores the address counter for write to a value before the unrequired frame is received to prepare the reception of the succeeding frame. Thus, only the required frame is stored continuously in the area at all times.
申请公布号 JPS63222549(A) 申请公布日期 1988.09.16
申请号 JP19870057323 申请日期 1987.03.11
申请人 NEC CORP 发明人 OTERU YOICHI
分类号 H04L13/08;G06F13/00;H04L13/18 主分类号 H04L13/08
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