| 摘要 |
PURPOSE:To avoid the peaking at each middle point, by dividing a filter into several filters and providing a circuit producing no peaking at the front stage. CONSTITUTION:The 1st BBDd consisting of 5 transistors Qd1-Qd5, the 2nd BBDe consisting of 6 transistors Qe1-Qe6, and the 3rd BBDf are provided. The signal supplied from the input terminal 1 is supplied to a serial circuit of the delay circuits 81 and 82 of Z<-1> forming the BBDd. This signal plus the outputs of the circuits 81 and 82 are supplied to the compounding device 86 for addition through the weighting circuits 83-85 having the coefficients D0, D2 and D4. The signal from the device 86 is supplied to a serial circuit of the delay circuits 87 and 88 of Z<-1> forming the BBDe. The outputs of the circuits 87 and 88 are supplied to the device 86 through the weighting circuits 89 and 90 having the coefficients E2 and E4 each to be subtracted from said addition signal. |
