| 摘要 |
In an arithmetic control unit according to the invention, which is a one-chip high density semiconductor integrated element capable of controlling the prefetching of user's instructions with respect to a main memory, an arithmetic logic unit (ALU) (220) effects the subtraction of the content of a location counter (208) holding the location of an user's instruction to be executed next from the content of a memory address register (206) holding main memory address data, and the result of the subtraction is discriminated through gates (308, 309) connected to the ALU for determing whether or not to make prefetched instruction buffer content ineffective. An address matching mechanism (300) provided outside the chip of the arithmetic control unit according to the invention includes a comparator (303) for comparing an execution stop address set by an address switch (301) and the memory addresses. The output data of the comparator (303) is stored in a particular memory section (203x) which is provided to correspond to the prefetched instruction buffer (203), and when a microinstruction stored in the prefetched instruction buffer (203) is tranferred to an instruction register (202), the data stored in the particular memory section (203x) is also read out to check for the execution stop address. Further, when making access to the main memory a particular signal indicating whether the access is pertinent is externally coupled and stored in the particular memory section (203x), so that it may be read out when reading out an instruction from the prefetched instruction buffer (203) and an illegal address interruption may be produced when it indicates that the access is inadequate. |
