发明名称 CYCLE TESTING CIRCUIT
摘要 PURPOSE:To add a function to a cycle test circuit to calculate many minimum polynomials at a high speed and with high efficiency, by using an m-stage shift register, a count circuit which counts the clocks of said shift register, a microcomputer, etc., to constitute the cycle test circuit. CONSTITUTION:A cycle test circuit consists of an m-stage shift register 1 (m=4), a microcomputer 2, a clock counter 3, AND circuits 4 and 6, a latch memory 5, a mono-multi 7 which transmits or prevents the clock signal to be applied to the register 1, and input/output ports 21-26 of the computer 2. In such a constitution, the value is doubled for each shift when a shift is performed to a high-order digit from a low-order one in response to each digit of the binary display numeric value at each stage of the register 1. While the value is halved when an adverse shift is carried out. Furthermore, an output signal existing at a carry terminal C of the register 1 is sent back to the least significant digit. Thus a ring counter is formed. That is, the relation of modulo (2<m>-1) is satisfied so that the real time processing is possible in such fields including the generation of random numbers, an experiment plan method, etc.
申请公布号 JPS63221424(A) 申请公布日期 1988.09.14
申请号 JP19870056337 申请日期 1987.03.10
申请人 NEC CORP;NIPPON DENKI MUSEN DENSHI KK 发明人 SATO TSUTOMU;OGURI KAZUO;HONMA TAKAMICHI;AOKI MASAJI;TSUNETOMI HIROSHI
分类号 G06F11/10;G06F7/58;H03M13/00 主分类号 G06F11/10
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