| 摘要 |
<p>PURPOSE:To surely generate a power-on reset signal by providing a grounded- source circuit stage provided with a resistive load element and an enhancement CMOS transistor(TR) and a CMOS inverter stage whose output stage connects to a capacitive load element. CONSTITUTION:The titled circuit consists of a 1st stage groundedsource circuit 51, a 2nd stage common source circuit 52 and a 3rd stage CMOS inverter 53. Drive transistors(TRs) 1, 2, 3, 4 of each stage are formed as the enhancement respectively. A drain voltage is fed back to the fate by connecting the drain and source of the TR 1 in the 1st stage grounded-source circuit 51 and the voltage at its output contact (a) is started after the power voltage exceeds a threshold voltage. Similarly, the 2nd stage grounded-source circuit 52 starts voltage rise, an output voltage of the 3rd stage inverter 53 is inputted to a Schmitt trigger 5, where the voltage is converted into binary information with a hysteresis.</p> |
