| 摘要 |
<p>A block access system using a cache memory comprises a first control circuit (12) for producing a block access request for requesting read-out of all data included in a block of a predetermined size in response to an access request from an operation unit (10) and inputting the data read out from a main memory unit (16) into a cache memory (13), and a second control circuit (15) for reading out data from the main memory unit and sending back to the first control circuit a response signal (BLACK) which indicates any one of execution and cancellation of the requested block access in response to a block access request (BLOCK) from the first control means. Memory addresses necessary for reading out all the data in one block are produced by the first control circuit when the block access request is cancelled. Alternatively, memory addresses are supplied by the second control circuit when the block access request is executed.</p> |
