| 摘要 |
<p>A timing recovery circuit includes a detector for detecting the varying points of a split-phase signal having a repeating logical "1" and "0" pattern at its beginning. A voltage-controlled oscillator (VCO) generates a signal whose frequency is twice as high as that of the timing signal of the split-phase signal and controls the frequency of the generated signal in response to a control signal. A frequency divider divides by two the output frequency of the VCO. A selector selectively supplies the output of the VCO and that of the frequency divider. A phase detector phase-compares the output of the varying point detector and that of the selector, and supplies the VCO with a signal indicating the relative delay or advance between the two outputs as the control signal. A control circuit controls the selector so that it selects the output of the frequency divider during the repetitive pattern of logical "1" and "0" and that of the VCO elsewhere. The invention permits large scale integration and permits the frame length of data to be large without requiring a highly stable oscillator.</p> |
