发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To shorten a synchronizing recovery time by supplying the synchronizing information of input data before the speed is converted as it is, to a timing pulse generating device of an output side with one more elastic store in a synchronizing circuit using the elastic store. CONSTITUTION:Synchronizing information FL of the low speed data before the speed conversion detected by an input side synchronizing detecting circuit 4 with a low speed clock fL is sent through an elastic store 5 to a high speed side timing pulse generating device 3b as it is. For this reason, even when a high speed side clock fH is temporarily turned off, the synchronizing information FL of input signal data is continued to be sent, and thus, when the high speed clock fH which is turned off is inputted again, the circuit can immediately enter the synchronizing condition.
申请公布号 JPS63220629(A) 申请公布日期 1988.09.13
申请号 JP19870053819 申请日期 1987.03.09
申请人 FUJITSU LTD 发明人 MORITAKA TETSUO;IKUTA KOJI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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