| 摘要 |
PURPOSE:To prevent the generation of malfunction due to noise included in an input signal by providing the titled device with three cascade latch circuits or more for latching an input signal synchronously with a sampling clock and a majority decision logic circuit having three inputs or more for inputting respective data signals from the latch circuits in parallel. CONSTITUTION:The titled circuit is provided with three cascade latch circuits or more 101-104 for latching an input signal synchronously with a sampling clock and the majority decision logic circuit 200 having three inputs or more for inputting respective data signals outputted from respective latch circuits 101-104 in parallel. When three or more out of data signals Q1-Q4 from respective D flip flops are high levels, the circuit 200 sets up data in an output data latch 301 to turn its output signal Q1 to a high level. Consequently, influence due to noise included in the input signal is not easily exerted and the generation of malfunction can be prevented. |
