| 摘要 |
PURPOSE:To prevent the leakage of the data of a memory cell by a method wherein a threshold voltage of a parasitic MIS transistor which is constituted by a first conductive layer, a buried layer and a semiconductor layer is set to be more than a half of the difference in level between a low logic-level value of a write voltage and its high logic-level value. CONSTITUTION:A threshold voltage of a parasitic MIS transistor Q2 which is constituted by a first conductive layer 8, a buried layer 2 and a semiconductor layer 3 is set to be more than a half of the difference in level between a low logic-level value of a write voltage and its high logic-level value. Accordingly, the parasitic MIS transistor Q2 is never turned on. That is to say, because a forward current does not flow to a second diode within a range of lower than a prescribed voltage, the leakage in the reverse direction is prevented and the leakage of the data of a memory cell is prevented. By this setup, the retention characteristics as a memory are enhanced. |
