发明名称 Multilayered printed circuit board type resistor isolated tray for stress testing integrated circuits and method of making same
摘要 An improved apparatus for stress testing a plurality of electronic circuits each formed on a wafer-like chip along at least one edge thereof and comprising a separate socket (60 of FIG. 1) having a set of contacts for receiving and holding one of the wafers with the set of contacts making contact with the edge contacts of the wafer it is holding and a plurality of terminal pins which are connected to the wafer edge contacts through the set of contacts and with the terminal pins of each socket being arranged in identical patterns. The apparatus comprises a multilayered printed circuit board (FIG. 4) having a plurality of identical groups of conductively plated holes (PTHs) (FIG. 15) formed therein for each socket and with each group of PTH's comprising the plurality of pin terminal holes (FIG. 15) arranged to receive the terminal pins of one of the sockets and a plurality of via holes (FIG. 15) formed therein around each socket to provide conduction between layers of said multilayered board for each socket and further with the via holes of each group of PTHs being of identical patterns, a plurality of printed circuit resistors (154 of FIG. 15) formed in one or more layers of the multilayered printed circuit board with each resistor being connected between a pin terminal hole and a via hole of the group of holes of each socket and exclusive of any other pin terminal hole or via hole with respect to connecting a resistor therebetween. Also provided is a plurality of conductive leads (lead 172 of FIG. 19 and lead 208 of FIG. 20) for connecting together the corresponding via holes of each of the sockets, and the corresponding via holes of each of the sockets, a plurality of signal sources (signal sources 1, 2, and 8 of FIG. 12) for supplying a unique signal to each group of corresponding via holes via a unique one of the conductive means, and a voltage source (+VCC and PGA of FIG. 12) for providing a common voltage source on a selected layer of the multilayered printed circuit board between selected ones of the plated through holes of each socket.
申请公布号 US4771236(A) 申请公布日期 1988.09.13
申请号 US19850809155 申请日期 1985.12.16
申请人 BANKS, SHERMAN M. 发明人 BANKS, SHERMAN M.
分类号 G01R31/316;H05K1/16;H05K3/42;H05K3/46;(IPC1-7):G01R31/02 主分类号 G01R31/316
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