| 摘要 |
PURPOSE:To simplify software and to make the contents of memories coincident by providing a means transferring all data of oneself to other memories by means of the transfer means of a common bus if a memory receives a transfer request and becomes a transfer source. CONSTITUTION:If a CPU5a reads data, data is read from a shared memory device 1a which is connected to the input output bus of oneself. If the CPU5a writes data in the shared memory, data is written only in the shared memory device 1a. When data is written at such a time, the shared memory device 1a holds an address and data at that time, and outputs a write request to the common bus 6 at a timing different from that the CPU5a writes. When the exclusive right of the common bus 6 is obtained, said device outputs the address and data which have been held on the common bus 6. Furthermore, it outputs the write signal and executes writing until all the shared memory device 1a-1d including oneself. Consequently, data in all the shared memory devices coincide after a prescribed time. |
