| 摘要 |
PURPOSE:To facilitate a test in a desired circuit part and to shorten a time for the test, by combining a plurality of parallel registers which can select an input. CONSTITUTION:A testing circuit is constituted by parallel registers 10, 20 and 30 comprising scan latch circuits 11-1n, 21-2n and 31-3n respectively, and a signal inputted to a terminal (a) or (b) is outputted selectively by a control signal C(C1-C3). Test data inputted to a terminal I1-In are taken in a circuit part 2a through the register 10 and subjected to processing therein, and then they are outputted to a terminal O1-On through the registers 20 and 30. As a result, it becomes possible to input the test data in parallel to a desired circuit part and to output processed data in parallel. |
