| 摘要 |
PURPOSE:To dispense with a parity arithmetic pulse generating circuit by providing a circuit calculating a vertical parity and a horizontal parity with respect to each corresponding bit of one frame of an input data, a circuit calculating the horizontal parity with respect to the vertical parity and a comparator detecting a parity error. CONSTITUTION:The vertical parity generating circuits 21a, 21b generates parity bits corresponding to odd/even number of 1s included in the bit corresponding to the data of plural channel. The horizontal parity generating circuits 22a, 22b generate a parity bit corresponding to odd/even number of 1s included in one frame of the parity bit outputted by the vertical parity generating circuits 21a, 21b. The vertical parity bit is generated in the bit corresponding to each channel in a frame and the horizontal parity bit with respect to the vertical parity bit is taken and compared with the comparator 4, then no problem arises even when a data processing section 1 applies any processing and a parity calculation pulse generating circuit in a conventional system is not required.
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