| 摘要 |
PURPOSE:To generate a stable reset signal independently of the rise time of a power waveform at the application of power and the scale of an integrated circuit by including an oscillating circuit high in operating start voltage and a counter capable of being initialized by its own performance. CONSTITUTION:When a power voltage reaches a potential V1 at the application of power, circuits 2, 3 except an oscillation circuit 1 start their operation, and the counter circuit 2 is initialized by a capacitor or the like. When the power voltage rises to a potential V2 succeedingly, the oscillation circuit 1 starts oscillation, the signal is received by the counter circuit 2, and when the preset count is reached, a NAND gate 3 stops the clock signal. Thus, a reset signal having a preset pulse width (count of counter circuit 2) is outputted stably independently of the rise time of a power waveform.
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