| 摘要 |
PURPOSE:To attain correct data transfer even when a continuous mode in changed to a single clock mode by storing a sending data into a buffer as the mode is transferred to the single mode, and supplying the result to a flip- flop. CONSTITUTION:Whether the mode is the consecutive clock mode outputting clocks consecutively or the single clock mode outputting clocks singly is identified and a control signal is generated by a mode identification circuit 4. Moreover, a buffer flip-flop 5 storing tentatively the transmission data and the changeover circuit 3 supplying sent data to the sending flip-flop 1 or the said buffer flip-flop 5 switchingly in response to the control signal are provided. As to the transition to the single clock mode, the transmission data is stored in the flip-flop 5 and inputted to the transmission flip-flop 1. Thus, even when the clock mode is changed from the consecutive mode into the single mode, the accurate data transfer without data missing is attained. |
