| 摘要 |
PURPOSE:To attain high speed decoding while using effectively storage capacity by providing a converter among M-set of pathmetrics, M-set of ACS arithmetic circuits and a path select signal generating circuit so as to operate the M-set of states at the same time, and to repeat said process for the plural number of times, thereby processing all states. CONSTITUTION:A switching signal generated by a switching signal generator is used to access the pathmetric corresponding to each state, and an address signal corresponding to two states in a unit cell is distributed to memories M17, M18 by a switch 18. The memories M1, M2 are accessed by addresses for the distributed M1, M2 to read pathmetrics alpha, beta. The ACS arithmetic operation is applied by using branchmetrics lambda1, lambda2, alpha, beta calculated depending on the reception signal to form the revision pathmetric. Then a revised pathmetric is being written to the memory M1 or M2 of the address. As a result, the operating speed is quickened and the scale of the hardware of the storage circuit is reduced.
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