| 摘要 |
<p>PURPOSE:To easily obtain an optional delay time or an optional pulse width by providing a delay circuit network comprising plural delay circuits, a multiplexer circuit outputting one of plural delay outputs selectively and a logic circuit receiving the output of the multiplexer circuit and an input signal and outputting the result of logic operation. CONSTITUTION:In giving, e.g., a negative pulse 11 to a pulse input terminal 1, a retarded pulse 12 in response to the delay time of the delay circuit 2 is outputted at the output of the delay circuit 2. A delay pulse 15 being the sum of delay times of delay circuits 2-5 is outputted at the output of the delay circuit 5. Each delay pulse is inputted to the multiplexer 6, where one delay pulse is selected. The delay time and the input pulse to the pulse input terminal 1 are ORed by a logic circuit 7, from which a negative pulse having a wider pulse width than that of the input pulse is outputted. In this case, the output pulse width is the sum of the delay time of the delay pulse to the input pulse width. When the delay pulse 15 is selected similarly, an output pulse 19 is outputted.</p> |
