| 摘要 |
PURPOSE:To reduce the collector parasitic capacitance and the base resistance of the title semiconductor device by a method wherein the positional relations between each of base, emitter and collector regions, and each of a lead-out layer, a buried region and a channel-cut region are determined by applying self-alignment. CONSTITUTION:An N<+> buried layer 23 and an N-epitaxial layer 24 are formed on a substrate 21, and an island is formed by etching on the area other than an element region as deep as it reached the substrate passing through the layers 23 and 24 using a multilayered insulating film consisting of an oxide film, a nitride film, an oxide film and a nitride film. Then, after a channel-cut layer 22 has been formed by implanting ions, a nitride film 29 is formed on the side face, and boron polysilicon is formed on the bottom part. Subsequently, an insulating film 25 is formed by etching leaving an N-type polysilicon 26 on the side face. Then, an oxide film 38 is formed on the surface of the N-type polysilicon, and a P-type polysilicon 27, which becomes a base lead-out layer, and electrodes 32, 33 and 34 are formed.
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