发明名称 MEMORY CONTROL CIRCUIT FOR ELECTRONIC RECEIVER
摘要 PURPOSE:To realize an optimum memory format even in any mode by making the designation of consecutive digit different between the calculation mode and the reception mode. CONSTITUTION:A control circuit 21 applies operation control or tuning control according to the key input from a key input section 22. A RAM 23 stores a data relating to the calculation or a data relating to the reception. The control circuit 21 designates to increment/decrement an address of the RAM 23 sequentially up to a prescribed stop address. When the reception mode is designated by the key input section 22, the stop address in the RAM 23 is changed to an address different from that at the calculation mode.
申请公布号 JPS63214861(A) 申请公布日期 1988.09.07
申请号 JP19870048086 申请日期 1987.03.03
申请人 CASIO COMPUT CO LTD 发明人 MOTO TAKASHI;KIZAKI MASAHARU
分类号 G06F15/02;H04B1/16 主分类号 G06F15/02
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