| 摘要 |
PURPOSE:To avoid the reduction of processing seed by writing the absence of an actual address detected during an address conversion into a comparatively high speed address converting buffer. CONSTITUTION:By a part of the virtual address inputted to a virtual address register 1, an address converting buffer 2 is addressed and a virtual address VA stored into an entry is inputted to a comparing logic circuit 6. Simultaneously, the contents of the register 1, an effective bit V showing the effectiveness of respective entries of the buffer 2 and a presence bit P showing the presence of the actual page corresponding to the virtual address are inputted to the circuit 6. When the circuit 6 judges that the actual address corresponding to the virtual address is registered to the buffer 2, an actual address PA is outputted. When it is not registered, the contents of an address converting table 4 are written into the buffer 2 by an address converting logic circuit 3.
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