| 摘要 |
<p>PURPOSE:To accelerate a processing, by using the most delayed address signal as the address signal of a decoder for a selector at the final stage of the output of a memory circuit. CONSTITUTION:The output signals M5'-M7' of the memory circuit for previous address signals are outputted to the outputs DX and DY of an X and Y bit memory circuit via DFF0'-DFF2' when a lock signal CLK1 is set at an H. The address signals J1' and J2' of a control circuit 20 become the input signals of the decoder 8, and generate the input signals Y0'-Y3' of the selector circuit 42. By setting the most delayed signal out of the address signals outputted at the control circuit 20 as the address signal of the decoder corresponding to the selector circuit at the final stage of the memory circuit 10, it is possible to heighten a clock frequency.</p> |
