| 摘要 |
PURPOSE:To accelerate an access time and a data transfer rate, by allocating a logic address at every number of bits equivalent to the number of minor loops,and transferring the next page to a position possible to be read out in a minimum time after completing access. CONSTITUTION:The 1st page address at the time of accessing a single page and a multipage is transferred a position where the next page can be read out in the minimum time after the access, that is in the neighborhood of a read major line RML. By performing an operation in such a way, when the next access is performed, since the page to be accessed exists in the neighborhood of the read major line RML, copying can be performed on the read major line RML in the minimum time, and the access time can be accelerated.
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