发明名称 Method of forming selective polysilicon wiring layer to source, drain and emitter regions by implantation through polysilicon layer
摘要 A method of manufacturing a semiconductor device, comprises the process of forming first and second well regions, which are of N-type and P-type, respectively, in a silicon body, forming a base layer of P-type in the first well region, forming an emitter layer of N-type in the base layer, forming source and drain layers of N-type in the second well region, forming a polysilicon emitter electrode on the emitter layer, and ion-implanting impurities of N-type into an interface between the emitter layer and the emitter electrode, so as to break down an insulative layer at the interface.
申请公布号 US4769337(A) 申请公布日期 1988.09.06
申请号 US19870047146 申请日期 1987.05.08
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MAEDA, TAKEO
分类号 H01L21/285;H01L21/336;(IPC1-7):H01L21/265;H01L21/22 主分类号 H01L21/285
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