| 摘要 |
PURPOSE:To manufacture the title memory cell proper to the improvement of the degree of integration without increasing resistance even when the occupying ratio of the main surface of a semiconductor substrate is reduced by forming at least either one of a source region and a drain region onto the side wall surface of a trench shaped to the semiconductor substrate. CONSTITUTION:A p-type semiconductor substrate 1 is etched through anisotropic etching such as reactive ion etching. Since an silicon nitride film 8 in the upper section of a gate electrode pattern funtions as a mask against said etching, a trench 14 with a side wall surface approximately continuing to the surface of the edge end section of a first gate insulating film 4 is shaped. The resist 8 is removed, and an n-type impurity is diffused to the side wall surface and base of the trench to form inter trench diffusion layers (source regions 3a, 3b and an n-type impurity layer 15). Various methods such as an impurity diffusion method by heat treatment in the atmosphere of a substance such as POCl3, an impurity diffusion method from the coating film of arsenic silicate glass, etc., can be used as the impurity diffusion method. Drain regions 2a, 2b may be shaped at the same time as the formation of the inter-trench diffusion layers or be shaped separately.
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