| 摘要 |
PURPOSE:To prevent a through-current from being caused to flow by retarding an internal input signal selectively so as to eliminate simultaneous ON-state of an output MOS transistor (TR). CONSTITUTION:The in-phase signal of an input signal phi1 via inverters 12, 13 is inputted to a switch TR 10 and an inverting signal via an inverter 14 is inputted to a gate of an n-channel MOS TR 9 of the switch TR 11. An output signal of the switch TR 11 is inputted to a gate of an n-channel MOS TR 8 of the switch TR 10 via an inverter 19. The similar connection exists also to the input signal phi2. In the case of the input signal transited from 'H' to 'L' level, the operation of a P-channel MOS TR 1 is retarded and in the case of the input signal transited from 'L' to 'H' level, the operation of the n- channel MOS TR 2 is retarded to eliminate simultaneous ON state. |
