| 摘要 |
PURPOSE:To eliminate impartiality of opportunities for processing among CPUs and to smoothly perform processings by successively changing priority levels of CPUs based on the transverse and longitudinal precedence set tables of a priority controller. CONSTITUTION:If request signals 110-112 are simultaneously sent from CPUs (a)-(c) to a priority controller, a permission signal 113 is sent to the CPU (a) in accordance with contents of a transverse precedence set table 1a. At this time, signals 111 and 112 of CPUs (b) and (c) having lower priority levels are moved to a hierarchy 11, and a precedence request bit is newly inputted to the table 1a of a hierarchy (i). Though the CPU (a) continuously requests the operation at this time, a permission signal 114 is sent to the CPU (b) because the precedence request bit is moved to the CPU (b) in the table 1a of a hierar chy (ii). Similarly, the signal 112 is moved to the hierarchy (iii) and a permission signal 115 is sent to the CPU (c). Thus, the unevenness of opportunities for processing is eliminated to smoothly perform processings. |
