| 摘要 |
PURPOSE:To restore and reproduce stably a digital signal and to attain a circuit constitution which can be converted easily into an IC, by controlling the pulse width of a binary code obtained by detecting the threshold value of the reproduced signal on the basis of the timing component extracted from the reproduced signal having approximately fixed peak value or mean value. CONSTITUTION:A ternary coded signal is extracted from an equalizer 33 after undergoing the optimum equalization of waveform through integration of characteristics of both equalizers 31 and 33. This ternary coded signal is supplied to a peak value detecting circuit 34, and the attenuation quantity (gain) of an AGC circuit 32 is variably controlled to be turned into a fixed amplitude so that the positive/negative peak value is set at a fixed level. Then a timing component extracting circuit 38 extracts the timing component (clock component). This timing component is supplied to a signal discriminating circuit 40 together with detection signals (c) and (d) which are delivered from a digital signal detecting circuit 36. Thus the pulse width is controlled, and the reproduced signal waveform of an original digital signal is extracted from a logical circuit 45. In such a constitution, a digital signal can be reproduced stably and approximately all circuit parts can be converted into a monolithic IC. |
