发明名称 TROUBLE DETECTION CIRCUIT AND TROUBLE DIAGNOSING FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To enable selection of trouble detection of two symbols or over contained in an input inspection pattern, by providing an exclusive OR circuit between respective stages of a plurality of feedback shift registers. CONSTITUTION:A circuit 1 to be inspected is a logical circuit and (n) results of inspection are outputted per time slot. A signature circuit 2 receives an input of the number (m) of 2-D systems from the circuit 1 being inspected and more than one feedback shift register (MISR), 4, 5, 6,... generate signatures S0, S1, S2,.... A trouble decision circuit 3 receives inputs of the signatures S0, S1, S2,... and judges that trouble is in the circuit 1 being inspected when all the signatures are zero. When one or more signatures are not zero, the circuit 1 being inspected is determined to cause a trouble. Here, the MISRs 4, 5, 6,... have exclusive OR circuits between respective stages thereof with an inspection pattern and outputs of a plurality of other stages or an output of down stage as inputs and detects errors up to (n) symbols.
申请公布号 JPS63210679(A) 申请公布日期 1988.09.01
申请号 JP19870042555 申请日期 1987.02.27
申请人 HITACHI LTD 发明人 IWASAKI KAZUHIKO;KAWASAKI IKUYA;ARAKAWA FUMIO
分类号 G01R31/317;G01R31/28 主分类号 G01R31/317
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