| 摘要 |
<p>Computer timing apparatus enables two redundant strobe or clock elements (11, 12) to produce a single stream of timing pulses (CLK*), without interruption, when both elements are operating normally, and when one element fails. The apparatus incorporates a multi-stable stage (21, 22, 23, 24) and an output logic stage (25, 26, 27). The multi-stable stage detects state transitions in the input signals (CLK1, CLK2) of each clock element and generates a corresponding clock-tracking signal (TRACK1, TRACK2) which can disable the output of the corresponding clock from propagating through the output logic. The output logic stage logically combines each clock signal (CLK1 or CLK2) with its corresponding clock-tracking signal (TRACK1 or TRACK2), and logically combines the resultant signal to produce a single stream of output signals (CLK*) responsive to a next transition produced by either of the two strobe or clock elements.</p> |
