CONDUCTIVITY-ENHANCED COMBINED LATERAL MOS/BIPOLAR TRANSCONDUCTIVITY-ENHANCED COMBINED LATERAL MOS/BIPOLAR TRANSISTOR ISTOR

摘要

A semiconductor device comprising a combined lateral MOS/bipolar transistor includes an intermediate semiconductor layer (16) of the same conductivity type as the channel region (20), which layer extends laterally from the channel region to beneath the drain contact region (24) of the device. Additionally, a floating semiconductor layer (14) of opposite conductivity type to that of the channel region (20) is provided between the intermediate layer (16) and the substrate (12) of the device. Both the intermediate layer (16) and the substrate (12) are relatively lightly doped, to effectively isolate the floating layer (14) from above and below. This structure substantially improves the operating characteristics of the device, thus permitting operation in both the source-follower and common-source modes, while also providing a compact structure which features a relatively low normalized "on" resistance.